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The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier.

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The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier.

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2006

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Conference paper

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Name:	Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings 2006
DBLP:	db/conf/aPcsac/aPcsac2006.html