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FPGA area reduction by multi-output function based sequential resynthesis.

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FPGA area reduction by multi-output function based sequential resynthesis.

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2008

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Conference paper

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Name:	Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 2008
DBLP:	db/conf/dac/dac2008.html