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Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.

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Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.

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2006

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Conference paper

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Name:	Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006 2006
DBLP:	db/conf/dac/dac2006.html