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A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor.

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A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor.

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1998

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Conference paper

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Name:	1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France 1998
DBLP:	db/conf/date/date1998.html