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Layout to Logic Defect Analysis for Hierarchical Test Generation.

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Layout to Logic Defect Analysis for Hierarchical Test Generation.

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2007

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Conference paper

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Name:	Proceedings of the 10th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007 2007
DBLP:	db/conf/ddecs/ddecs2007.html