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Area minimization algorithm for parallel prefix adders under bitwise delay constraints.

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    Title: Area minimization algorithm for parallel prefix adders under bitwise delay constraints.
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    Date: 2007
    Publication type: Conference paper
    Authors:
    No. First name Last name Show
    1. Taeko Matsunaga
    2. Yusuke Matsunaga
    Download (by DOI): 10.1145/1228784.1228886
    BibTeX: conf/glvlsi/MatsunagaM07
    DBLP: db/conf/glvlsi/glvlsi2007.html#MatsunagaM07
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    Conference
    Name: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 2007
    DBLP: db/conf/glvlsi/glvlsi2007.html