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    Author information
    First name: Shaolei
    Last name: Quan
    DBLP: 08/334
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    Below you find the publications which have been written by this author.

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    Shaolei Quan, Qiang Qiang, Chin-Long Wey.
    Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test.
    14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India 2005 (0) 2005
    Shaolei Quan, Meng-Yao Liu, Chin-Long Wey.
    Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.
    20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA 2005 (0) 2005
    Shaolei Quan, Qiang Qiang, Chin-Long Wey.
    A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing.
    International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan 2005 (0) 2005
    Shaolei Quan, Chin-Long Wey.
    A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors.
    Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004 2004 (0) 2004
    Cheong Kun, Shaolei Quan, Andrew Mason.
    A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead.
    ISCAS (2) 2004 (0) 2004

    Your query returned 5 matches in the database.