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First name:	Jean Michel
Last name:	Portal
DBLP:	08/4890
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Show	Title	Venue	Rating	Date
	Olivier Ginez, Jean Michel Portal, Hassen Aziza. An on-line testing scheme for repairing purposes in Flash memories.	Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic 2009	(0)	2009
	Manuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy. Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework.	9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA 2008	(0)	2008
	Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean Michel Portal. Metal filling impact on standard cells: definition of the metal fill corner concept.	Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008 2008	(0)	2008
	Laurent Lopez, Jean Michel Portal, Didier Née. A New Embedded Measurement Structure for eDRAM Capacitor	CoRR 2007, Volume 0	(0)	2007
	B. Saillet, A. Regnier, Jean Michel Portal, B. Delsuc, R. Laffont, Pascal Masson, Rachid Bouchakour. MM11 based flash memory cell model including characterization procedure.	International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece 2006	(0)	2006
	Laurent Lopez, Jean Michel Portal, Didier Née. A New Embedded Measurement Structure for eDRAM Capacitor.	2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany 2005	(0)	2005
	B. Saillet, Jean Michel Portal, Didier Née. Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring.	20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA 2005	(0)	2005
	Jean Michel Portal, Hassen Aziza, Didier Née. EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement.	J. Electronic Testing 2005, Volume 21	(0)	2005
	S. Bernardini, Jean Michel Portal, Pascal Masson. A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology.	2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France 2004	(0)	2004
	Anna Labbé, Annie Pérez, Jean Michel Portal. Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture.	ISCAS (2) 2004	(0)	2004
	L. Forli, Jean Michel Portal, Didier Née, Bertrand Borot. Infrastructure IP for Back-End Yield Improvement.	Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA 2003	(0)	2003
	Jean Michel Portal, Hassen Aziza, Didier Née. EEPROM Memory: Threshold Voltage Built In Self Diagnosis.	Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA 2003	(0)	2003
	Jean Michel Portal, L. Forli, Didier Née. Floating-gate EEPROM cell: threshold voltage sensibility to geometry.	ISCAS (1) 2002	(0)	2002
	Jean Michel Portal, L. Forli, Didier Née. Floating-gate EEPROM cell model based on MOS model 9.	ISCAS (3) 2002	(0)	2002
	Jean Michel Portal, L. Forli, Hassen Aziza, Didier Née. An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell.	Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002 2002	(0)	2002
	Jean Michel Portal, L. Forli, Hassen Aziza, Didier Née. An Automated Design Methodology for EEPROM Cell (ADE).	10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France 2002	(0)	2002
	Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian. IS-FPGA : a new symmetric FPGA architecture with implicit scan.	Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001 2001	(0)	2001
	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian. A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.	J. Electronic Testing 2001, Volume 17	(0)	2001
	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian. TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan 2000	(0)	2000
	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. Testing the Local Interconnect Resources of SRAM-Based FPGA's.	J. Electronic Testing 2000, Volume 16	(0)	2000
	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.	J. Electronic Testing 2000, Volume 16	(0)	2000
	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. Minimizing the Number of Test Configurations for Different FPGA Families.	8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China 1999	(0)	1999
	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.	1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany 1999	(0)	1999
	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electronic Testing 1999, Volume 14	(0)	1999
	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.	7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore 1998	(0)	1998

Your query returned 31 matches in the database.