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    Author information
    First name: Minas
    Last name: Dasygenis
    DBLP: 23/5963
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    Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis.
    A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
    CoRR 2007, Volume 0 (0) 2007
    Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis.
    A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
    IEEE Trans. VLSI Syst. 2006, Volume 14 (0) 2006
    Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Adonios Thanailakis.
    Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.
    VLSI Signal Processing 2006, Volume 44 (0) 2006
    Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis.
    A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
    2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany 2005 (0) 2005
    Nikolas Kroupis, Minas Dasygenis, K. Markou, Dimitrios Soudris, Adonios Thanailakis.
    A modified spiral search motion estimation algorithm and its embedded system implementation.
    International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan 2005 (0) 2005
    Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis.
    Improving the Memory Bandwidth Utilization Using Loop Transformations.
    Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings 2005 (0) 2005
    Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Adonios Thanailakis.
    A Modified Spiral Search Algorithm and its Embedded Hardware Implementation.
    International Enformatika Conference, IEC'05, August 26-28, 2005, Prague, Czech Republic, CDROM 2005 (0) 2005
    Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis.
    Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
    Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings 2004 (0) 2004
    Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Adonios Thanailakis.
    Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms.
    Real-Time Imaging 2003, Volume 9 (0) 2003
    Nikolaos D. Zervas, G. Pagkless, Minas Dasygenis, Dimitrios Soudris.
    Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors.
    Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 2002 (0) 2002
    Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis.
    Power, performance and area exploration of block matching algorithms mapped on programmable processors.
    ICIP (3) 2001 (0) 2001
    Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas.
    Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1.
    2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA 2001 (0) 2001
    Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis.
    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.
    Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings 2000 (0) 2000

    Your query returned 13 matches in the database.