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First name:	Dipankar
Last name:	Sarkar
DBLP:	32/6411
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Show	Title	Venue	Rating	Date
	Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, P. Kumar. An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems 2008, Volume 27	(0)	2008
	Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade. Hand-in-hand verification of high-level synthesis.	Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 2007	(0)	2007
	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade. Register Sharing Verification During Data-Path Synthesis.	2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 5-7 March 2007, Kolkata, India 2007	(0)	2007
	Prodip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu. Fault diagnosis in discrete time hybrid systems - A case study.	Inf. Sci. 2007, Volume 177	(0)	2007
	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. A Formal Verification Method of Scheduling in High-level Synthesis.	7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA 2006	(0)	2006
	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. Verification of Scheduling in High-level Synthesis.	2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany 2006	(0)	2006
	Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay. Model checking on state transition diagram.	Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 2004	(0)	2004
	Dipankar Sarkar. Status Condition Analysis during Data Path Verification of Sequential Circuits.	13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India 2000	(0)	2000

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