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First name:	Ajit
Last name:	Pal
DBLP:	37/1732
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Show	Title	Venue	Rating	Date
	Ajit Pal, Santanu Chattopadhyay. Synthesis Testing for Low Power.	VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009 2009	(0)	2009
	Sudip Roy, Ajit Pal. Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?	11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008 2008	(0)	2008
	Tanmay De, Ajit Pal, Indranil Sengupta. Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning.	Distributed Computing and Networking, 9th International Conference, ICDCN 2008, Kolkata, India, January 5-8, 2008. 2008	(0)	2008
	Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta. A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks.	Proceedings of the 16th International Conference on Networks, ICON 2008, December 12-14, 2008, held at India Habitat Centre, New Delhi, India 2008	(0)	2008
	Sujan Kundu, Sudip Roy, Ajit Pal. A power-aware wireless sensor network based bridge monitoring system.	Proceedings of the 16th International Conference on Networks, ICON 2008, December 12-14, 2008, held at India Habitat Centre, New Delhi, India 2008	(0)	2008
	Akepati Sravan, Sujan Kundu, Ajit Pal. Low Power Sensor Node for a Wireless Sensor Network.	20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India 2007	(0)	2007
	Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya. On finding the minimum test set of a BDD-based circuit.	Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 2006	(0)	2006
	Gopal Paul, S. N. Pradhan, Ajit Pal, Bhargab B. Bhattacharya. Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.	IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006 2006	(0)	2006
	Ajit Pal, Umesh Patel. Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks.	Distributed Computing - IWDC 2004, 6th International Workshop, Kolkata, India, December 27-30, 2004, Proceedings 2004	(0)	2004
	Maitrali Marik, Ajit Pal. Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs.	17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India 2004	(0)	2004
	Debasis Samanta, Ajit Pal. Synthesis of Low Power High Performance Dual-VT PTL Circuits.	17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India 2004	(0)	2004
	Debasis Samanta, Ajit Pal. Synthesis of Dual-VT Dynamic CMOS Circuits.	16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India 2003	(0)	2003
	Debasis Samanta, Ajit Pal. Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.	Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India 2002	(0)	2002
	Debasis Samanta, Nishant Sinha, Ajit Pal. Synthesis of High Performance Low Power Dynamic CMOS Circuits.	Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India 2002	(0)	2002
	Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal. Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits.	14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India 2001	(0)	2001
	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal. An algorithm for finding a non-trivial lower bound for channel routing1.	Integration 1998, Volume 25	(0)	1998
	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal. An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.	10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India 1997	(0)	1997
	Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal. A general graph theoretic framework for multi-layer channel routing.	8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India 1995	(0)	1995
	Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal. Computing area and wire length efficient routes for channels.	8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India 1995	(0)	1995
	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta. NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic.	VLSI Design 1993	(0)	1993
	Ajit Pal. An Algorithm for Optimal Logic Design Using Multiplexers.	IEEE Trans. Computers 1986, Volume 35	(0)	1986

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