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First name:	Masahiro
Last name:	Ishida
DBLP:	43/2612
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	Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma. An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter.	International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA 2007	(0)	2007
	Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai. A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems.	Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA 2003	(0)	2004
	Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida. Skew measurements in clock distribution circuits using an analytic signal method.	IEEE Trans. on CAD of Integrated Circuits and Systems 2004, Volume 23	(0)	2004
	Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha. Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements.	Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA 2003	(0)	2003
	Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha. Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division.	J. Electronic Testing 2003, Volume 19	(0)	2003
	Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha. Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices.	11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA 2002	(0)	2002
	Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie. A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter.	Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002 2002	(0)	2002
	Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha. Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division.	20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA 2002	(0)	2002
	Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi. A Method for Compressing Test Data Based on Burrows-Wheeler Transformation.	IEEE Trans. Computers 2002, Volume 51	(0)	2002
	Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida. Testing clock distribution circuits using an analytic signal method.	Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001 2001	(0)	2001

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