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    Author information
    First name: Tianzhou
    Last name: Chen
    Company: Zhejiang university
    DBLP: 45/3043
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    Below you find the publications which have been written by this author.

    Show item 1 to 25 of 176  
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    Conference paper
    Ming Chen, John M. Ye, Tianzhou Chen, Hongjun Dai.
    Shared write buffer to boost applications on SpMT architecture.
    The Journal of Supercomputing 2017, Volume 73 (0) 2017
    Conference paper
    Licheng Yu, Yulong Pei, Tianzhou Chen, Xueqing Lou, Minghui Wu, Tiefei Zhang.
    Enable back memory and global synchronization on LLC buffer.
    The Journal of Supercomputing 2017, Volume 73 (0) 2017
    Journal article
    Licheng Yu, Yulong Pei, Tianzhou Chen, Minghui Wu.
    Architecture supported register stash for GPGPU.
    J. Parallel Distrib. Comput. 2016, Volume 89 (0) 2016
    Conference paper
    Licheng Yu, Yulong Pei, Tianzhou Chen, Xueqing Lou, Minghui Wu, Tiefei Zhang.
    LLC Buffer for Arbitrary Data Sharing in Heterogeneous Systems.
    18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2016, Sydney, Australia, December 12-1 2016 (0) 2016
    Conference paper
    Minghui Wu, Yulong Pei, Licheng Yu, Tianzhou Chen, Xueqing Lou, Tiefei Zhang.
    WAP: The Warp Feature Aware Prefetching Method for LLC on CPU-GPU Heterogeneous Architecture.
    18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2016, Sydney, Australia, December 12-1 2016 (0) 2016
    Conference paper
    Yulong Pei, Licheng Yu, Minghui Wu, Tianzhou Chen, Xueqing Lou, Tiefei Zhang.
    Two Methods for Combining Original Memory Access Coalescing and Equivalent Memory Access Coalescing on GPGPU.
    13th International Conference on Embedded Software and Systems, ICESS 2016, Chengdu, China, August 13-14, 2016 2016 (0) 2016
    Journal article
    Jianliang Ma, Licheng Yu, John M. Ye, Tianzhou Chen.
    MCMG simulator: A unified simulation framework for CPU and graphic GPU.
    J. Comput. Syst. Sci. 2015, Volume 81 (0) 2015
    Conference paper
    Tiefei Zhang, Jixiang Zhu, Jun Fu, Tianzhou Chen.
    CWC: A Companion Write Cache for Energy-Aware Multi-Level Spin-Transfer Torque RAM Cache Design.
    Journal of Circuits, Systems, and Computers 2015, Volume 24 (0) 2015
    Conference paper
    Jianliang Ma, Licheng Yu, Tianzhou Chen, Minghui Wu.
    Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture.
    14th International Symposium on Parallel and Distributed Computing, ISPDC 2015, Limassol, Cyprus, June 29 - July 2, 2015 2015 (0) 2015
    Conference paper
    Tiefei Zhang, Jianguo Xing, Jixiang Zhu, Tianzhou Chen.
    Exploiting Page Write Pattern for Power Management of Hybrid DRAM/PRAM Memory System.
    J. Inf. Sci. Eng. 2015, Volume 31 (0) 2015
    Conference paper
    Songyuan Li, Jinglei Meng, Licheng Yu, Jianliang Ma, Tianzhou Chen, Minghui Wu.
    Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System.
    17th IEEE International Conference on High Performance Computing and Communications, HPCC 2015, 7th IEEE International Symposium on Cyberspace Safety and Security, CSS 2015, and 12th IEEE International Conference on Embedded Software and Systems, ICESS 20 2015 (0) 2015
    Conference paper
    John M. Ye, Songyuan Li, Tianzhou Chen.
    Shared Write Buffer to Support Data Sharing Among Speculative Multi-threading Cores.
    17th IEEE International Conference on High Performance Computing and Communications, HPCC 2015, 7th IEEE International Symposium on Cyberspace Safety and Security, CSS 2015, and 12th IEEE International Conference on Embedded Software and Systems, ICESS 20 2015 (0) 2015
    Conference paper
    Hongjun Dai, Chao Yan, Bin Gong, Zhun Yang, Tianzhou Chen.
    Exploring Predictable Redundant Instruction Parallelism in Fault Tolerant Microprocessors.
    17th IEEE International Conference on High Performance Computing and Communications, HPCC 2015, 7th IEEE International Symposium on Cyberspace Safety and Security, CSS 2015, and 12th IEEE International Conference on Embedded Software and Systems, ICESS 20 2015 (0) 2015
    Conference paper
    Yulong Pei, Licheng Yu, Minghui Wu, Tianzhou Chen.
    Equidistant Memory Access Coalescing on GPGPU.
    17th IEEE International Conference on High Performance Computing and Communications, HPCC 2015, 7th IEEE International Symposium on Cyberspace Safety and Security, CSS 2015, and 12th IEEE International Conference on Embedded Software and Systems, ICESS 20 2015 (0) 2015
    Conference paper
    John M. Ye, Hongjun Dai, Songyuan Li, Tianzhou Chen.
    Shared Write Buffer to Support Speculative Execution.
    17th IEEE International Conference on High Performance Computing and Communications, HPCC 2015, 7th IEEE International Symposium on Cyberspace Safety and Security, CSS 2015, and 12th IEEE International Conference on Embedded Software and Systems, ICESS 20 2015 (0) 2015
    Conference paper
    Jianliang Ma, Tianzhou Chen, Minghui Wu.
    Making GPU Warp Scheduler and Memory Scheduler Synchronization-Aware.
    Cloud Computing and Big Data - Second International Conference, CloudCom-Asia 2015, Huangshan, China, June 17-19, 2015, Revised Selected Papers 2015 (0) 2015
    Conference paper
    Weiwei Fu, Li Liu 0006, Tianzhou Chen.
    Direct distributed memory access for CMPs.
    J. Parallel Distrib. Comput. 2014, Volume 74 (0) 2014
    Conference paper
    Weiwei Fu, Mingmin Yuan, Tianzhou Chen, Li Liu.
    An Exploration of Page Replication for NoC-Based On-Chip Distributed Memory Systems.
    22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014, Torino, Italy, February 12-14, 2014 2014 (0) 2014
    Conference paper
    John M. Ye, Hui Yan, Honglun Hou, Tianzhou Chen.
    Potential thread-level-parallelism exploration with superblock reordering.
    Computing 2014, Volume 96 (0) 2014
    Conference paper
    Like Yan, Binbin Wu, Yuan Wen, Shaobin Zhang, Tianzhou Chen.
    A reconfigurable processor architecture combining multi-core and reconfigurable processing units.
    Telecommunication Systems 2014, Volume 55 (0) 2014
    Conference paper
    Licheng Yu, Xingsheng Tang, Minghui Wu, Tianzhou Chen.
    Improving branch divergence performance on GPGPU with a new PDOM stack and multi-level warp scheduling.
    Journal of Systems Architecture - Embedded Systems Design 2014, Volume 60 (0) 2014
    Conference paper
    Tianzhou Chen, Weiwei Fu, Bin Xie 0002, Chao Wang 0001.
    Packet triggered prediction based task migration for network-on-chip.
    Microprocessors and Microsystems - Embedded Hardware Design 2014, Volume 38 (0) 2014
    Conference paper
    Weiwei Fu, Tianzhou Chen, Chao Wang 0001, Li Liu.
    Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems.
    The Journal of Supercomputing 2014, Volume 69 (0) 2014
    Conference paper
    Weiwei Fu, Mingmin Yuan, Tianzhou Chen, Minghui Wu.
    Design and Evaluation of Virtual Channel-Based Optical-Electrical Interface for Optical Network-on-Chip.
    14th IEEE International Conference on Computer and Information Technology, CIT 2014, Xi'an, China, September 11-13, 2014 2014 (0) 2014
    Conference paper
    Weiwei Fu, Mingmin Yuan, Tianzhou Chen, Li Liu.
    Agent-Based Memory Access for Many-Core CMPs.
    IEEE 13th International Symposium on Parallel and Distributed Computing, ISPDC 2014, Marseille, France, June 24-27, 2014 2014 (0) 2014
    Show item 1 to 25 of 176  

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