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    Author information
    First name: Hans
    Last name: Eveking
    DBLP: 50/5325
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    Below you find the publications which have been written by this author.

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    Martin Oberkönig, Martin Schickel, Hans Eveking.
    A Quantitative Completeness Analysis for Property-Sets.
    Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings 2007 (0) 2007
    Hans Eveking, Martin Oberkönig, Martin Schickel, Martin Schweikert, Volker Nimbler.
    Multi-Level Assertion-Based Design.
    5th ACM IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30 - June 1st, Nice, France 2007 (0) 2007
    Martin Schickel, Martin Oberkönig, Martin Schweikert, Hans Eveking.
    A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set.
    Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings 2007 (0) 2007
    Martin Schickel, Volker Nimbler, Martin Oberkönig, Hans Eveking.
    On Consistency and Completeness of Property-Sets.
    Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings 2006 (0) 2006
    Gerd Ritter, Holger Hinrichsen, Hans Eveking.
    Formal Verification of Descriptions with Distinct Order of Memory Operations.
    Advances in Computing Science - ASIAN'99, 5th Asian Computing Science Conference, Phuket, Thailand, December 10-12, 1999, Proceedings 1999 (0) 1999
    Gerd Ritter, Hans Eveking, Holger Hinrichsen.
    Formal Verification of Designs with Complex Control by Symbolic Simulation.
    Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings 1999 (0) 1999
    Hans Eveking, Holger Hinrichsen, Gerd Ritter.
    Automatic Verification of Scheduling Results in High-Level Synthesis.
    1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany 1999 (0) 1999
    Hans Eveking.
    (V)HDL-based verification of heterogeneous synchronous/asynchronous systems.
    Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994 1994 (0) 1994
    Hans Eveking, Stefan Höreth.
    Optimization and Resynthesis of Complex Data-Paths.
    DAC 1993 (0) 1993
    Hans Eveking.
    Automatic Verification of Extensions of Hardware Descriptions.
    Computer Aided Verification, 2nd International Workshop, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990, Proceedings 1991 (0) 1990

    Your query returned 11 matches in the database.