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First name:	Andrew R.
Last name:	Pleszkun
DBLP:	58/6514
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Show	Title	Venue	Rating	Date
	Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, Jesse Willek. A Performance Analysis of the iSCSI Protocol.	IEEE Symposium on Mass Storage Systems 2003	(0)	2003
	Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun. Confidence Estimation for Speculation Control.	ISCA 1998	(0)	1998
	James E. Smith, Andrew R. Pleszkun. Implementation of Precise Interupts in Pipelined Processors.	25 Years ISCA: Retrospectives and Reprints 1998	(0)	1998
	Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun. A modified approach to data cache management.	Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995 1995	(0)	1995
	Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun. A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.	ISCA 1994	(0)	1994
	Andrew R. Pleszkun. Techniques for compressing program address traces.	Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994 1994	(0)	1994
	Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun. MISC: a Multiple Instruction Stream Computer.	Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, November 1992 1992	(0)	1992
	Matthew K. Farrens, Andrew R. Pleszkun. Strategies for Achieving Improved Processor Throughput.	ISCA 1991	(0)	1991
	Matthew K. Farrens, Andrew R. Pleszkun. Implementation of the PIPE Processor.	IEEE Computer 1991, Volume 24	(0)	1991
	Matthew K. Farrens, Andrew R. Pleszkun. An evaluation of functional unit lengths for single-chip processors.	Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990 1990	(0)	1990
	Matthew K. Farrens, Andrew R. Pleszkun. Improving Performance of Small On-Chip Instruction Caches.	ISCA 1989	(0)	1989
	Andrew R. Pleszkun, Gurindar S. Sohi. The Performance Potential of Multiple Functional Unit Processors.	ISCA 1988	(0)	1988
	Andrew R. Pleszkun, Gurindar S. Sohi. Multiple instruction issue and single-chip processors.	Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988 1988	(0)	1988
	James E. Smith, Andrew R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors.	IEEE Trans. Computers 1988, Volume 37	(0)	1988
	Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter. WISQ: A Restartable Architecture Using Queues.	ISCA 1987	(0)	1987
	Andrew R. Pleszkun, Matthew Thazhuthaveetil. The Architecture of Lisp Machines.	IEEE Computer 1987, Volume 20	(0)	1987
	Matthew Thazhuthaveetil, Andrew R. Pleszkun. On the Structural Locality of Reference in LISP List Access Streams.	Inf. Process. Lett. 1987, Volume 26	(0)	1987
	Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson. Features of the Structured Memory Access (SMA) Architecture.	Spring COMPCON'86, Digest of Papers, Thirty-First IEEE Computer Society International Conference, San Francisco, California, USA, March 3-6, 1986 1986	(0)	1986
	Andrew R. Pleszkun, Matthew Thazhuthaveetil. An Architecture for Efficient Lisp List Access.	ISCA 1986	(0)	1986
	George E. Bier, Andrew R. Pleszkun. An algorithm for design rule checking on a multiprocessor.	Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA 1985	(0)	1985
	James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young. PIPE: A VLSI Decoupled Architecture.	ISCA 1985	(0)	1985
	James E. Smith, Andrew R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors.	ISCA 1985	(0)	1985
	Andrew R. Pleszkun, Edward S. Davidson. Structured Memory Access Architecture.	International Conference on Parallel Processing, ICPP'83, Columbus, Ohio, USA, August 1983 1983	(0)	1983

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