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First name:	Vijay S.
Last name:	Iyengar
DBLP:	60/6657
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	Matthew Hill, Murray Campbell, Yuan-Chi Chang, Vijay S. Iyengar. Event detection in sensor networks for modern oil fields.	Proceedings of the Second International Conference on Distributed Event-Based Systems, DEBS 2008, Rome, Italy, July 1-4, 2008 2008	(0)	2008
	Vijay S. Iyengar, Ioana Boier, Karen Kelley, Raymond Curatolo. Analytics for Audit and Business Controls in Corporate Travel and Entertainment.	Data Mining and Analytics 2007, Proceedings of the Sixth Australasian Data Mining Conference (AusDM 2007), Gold Coast, Queensland, Australia, December 3-4, 2007, Proceedings 2007	(0)	2007
	Vijay S. Iyengar, David Flaxer, Anil Nigam, John Vergo. Evaluation of IT Portfolio Options by Linking to Business Services.	Data Engineering Issues in E-Commerce and Services, Second International Workshop, DEECS 2006, San Francisco, CA, USA, June 26, 2006, Proceedings 2006	(0)	2006
	Vijay S. Iyengar. On detecting space-time clusters.	Proceedings of the Tenth ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, Seattle, Washington, USA, August 22-25, 2004 2004	(0)	2004
	Vijay S. Iyengar. Transforming data to satisfy privacy constraints.	Proceedings of the Eighth ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, July 23-26, 2002, Edmonton, Alberta, Canada 2002	(0)	2002
	Tong Zhang, Vijay S. Iyengar. Recommender Systems Using Linear Classifier.	Journal of Machine Learning Research 2002, Volume 2	(0)	2002
	Vijay S. Iyengar, Tong Zhang. Empirical Study of Recommender Systems Using Linear Classifiers.	Knowledge Discovery and Data Mining - PAKDD 2001, 5th Pacific-Asia Conference, Hong Kong, China, April 16-18, 2001, Proceedings 2001	(0)	2001
	Vijay S. Iyengar, Jon Lee, Murray Campbell. Evaluating multiple attribute items using queries.	Proceedings 3rd ACM Conference on Electronic Commerce (EC-2001), Tampa, Florida, USA, October 14-17, 2001 2001	(0)	2001
	Vijay S. Iyengar, Chidanand Apté, Tong Zhang. Active learning using adaptive resampling.	KDD 2000	(0)	2000
	Vijay S. Iyengar. HOT: Heuristics for Oblique Trees.	ICTAI 1999	(0)	1999
	Vijay S. Iyengar, Louise Trevillyan, Pradip Bose. Representative Traces for Processor Models with Infinite Cache.	HPCA 1996	(0)	1996
	Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal. AVPGEN-A test generator for architecture verification.	IEEE Trans. VLSI Syst. 1995, Volume 3	(0)	1995
	Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen. Architectural Verification of Processors Using Symbolic Instruction Graphs.	Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994 1994	(0)	1994
	Daniel Brand, Vijay S. Iyengar. Identification of redundant delay faults.	IEEE Trans. on CAD of Integrated Circuits and Systems 1994, Volume 13	(0)	1994
	Daniel Brand, Vijay S. Iyengar. Identification of Single Gate Delay Fault Redundancies.	Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992 1992	(0)	1992
	Ashok K. Chandra, Vijay S. Iyengar. Constraint Slving for Test Case Generation.	Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992 1992	(0)	1992
	Yaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen. AC Test Quality: Beyond Transition Fault Coverage.	Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992 1992	(0)	1992
	Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams. Delay Test: The Next Frontier for LSSD Test Systems.	Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992 1992	(0)	1992
	Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy. A Small Test Generator for Large Designs.	Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992 1992	(0)	1992
	Vijay S. Iyengar, Gopalakrishnan Vijayan. Optimized test application timing for AC test.	IEEE Trans. on CAD of Integrated Circuits and Systems 1992, Volume 11	(0)	1992
	Vijay S. Iyengar, Gopalakrishnan Vijayan. Test Application Timing: The Unexplored Issue in AC Test.	Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991 1991	(0)	1991
	Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski. On computing the sizes of detected delay faults.	IEEE Trans. on CAD of Integrated Circuits and Systems 1990, Volume 9	(0)	1990
	Daniel Brand, Vijay S. Iyengar. Synthesis of Pseudo-Random Pattern Testable Designs.	Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989 1989	(0)	1989
	Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger. Delay Test Generation 1: Concepts and Coverage Metrics.	Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988 1988	(0)	1988
	Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger. Delay Test Generation 2: Algebra and Algorithms.	Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988 1988	(0)	1988
	Daniel Brand, Vijay S. Iyengar. Timing Analysis Using Functional Analysis.	IEEE Trans. Computers 1988, Volume 37	(0)	1988
	Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman. SLS-a fast switch-level simulator [for MOS].	IEEE Trans. on CAD of Integrated Circuits and Systems 1988, Volume 7	(0)	1988
	Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman. SLS - a fast switch level simulator for verification and fault coverage analysis.	DAC 1986	(0)	1986
	Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman. Efficient Fault Simulation of CMOS Circuits with Accurate Models.	Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986 1986	(0)	1986
	John A. Waicukauski, Eric Lindbloom, Vijay S. Iyengar, Barry K. Rosen. Transition Fault Simulation by Parallel Pattern Single Fault Propagation.	Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986 1986	(0)	1986
	Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman. Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits.	Proceedings International Test Conference 1985, Philadelphia, PA, USA, November 1985 1985	(0)	1985
	Vijay S. Iyengar, Larry L. Kinney. Concurrent Fault Detection in Microprogrammed Control Units.	IEEE Trans. Computers 1985, Volume 34	(0)	1985
	Vijay S. Iyengar, Larry L. Kinney. Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units.	Proceedings International Test Conference 1982, Philadelphia, PA, USA, November 1982 1982	(0)	1982

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