Publications :: Search

Show author

On this page you see the details of the selected author.

Author information
First name:	Naveen
Last name:	Muralimanohar
DBLP:	74/2786
Rating:	(not rated yet)
Bookmark:

Below you find the publications which have been written by this author.

Show item 1 to 10 of 10  

Select a publication
Show	Title	Venue	Rating	Date
	Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell. Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.	15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA 2009	(0)	2009
	Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie. Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.	Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA 2009	(0)	2009
	Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian. Scalable and reliable communication for hardware transactional memory.	17th International Conference on Parallel Architecture and Compilation Techniques (PACT 2008), Toronto, Ontario, Canada, October 25-29, 2008 2008	(0)	2008
	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi. Architecting Efficient Interconnects for Large Caches with CACTI 6.0.	IEEE Micro 2008, Volume 28	(0)	2008
	Naveen Muralimanohar, Rajeev Balasubramonian. Interconnect design considerations for large NUCA caches.	34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA 2007	(0)	2007
	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA 2007	(0)	2007
	Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter. Interconnect-Aware Coherence Protocols for Chip Multiprocessors.	33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA 2006	(0)	2006
	Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian. Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.	2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings 2006	(0)	2006
	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter. Leveraging Wire Properties at the Microarchitecture Level.	IEEE Micro 2006, Volume 26	(0)	2006
	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy. Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA 2005	(0)	2005

Your query returned 10 matches in the database.