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First name:	Katsumasa
Last name:	Watanabe
DBLP:	84/5727
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Show	Title	Venue	Rating	Date
	Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe. Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles.	IEICE Transactions 2007, Volume 90	(0)	2007
	Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe. Robust Quantum Algorithms with	Computing and Combinatorics, 12th Annual International Conference, COCOON 2006, Taipei, Taiwan, August 15-18, 2006, Proceedings 2006	(0)	2006
	Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe. An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs.	IEICE Transactions 2006, Volume 89	(0)	2006
	Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita. Event-oriented computing with reconfigurable platform.	Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005 2005	(0)	2005
	Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe. Reconfigurable 1-Bit Processor Array with Reduced Wirng Area.	Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 2005	(0)	2005
	Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe. A real-time 64-monosyllable recognition LSI with learning mechanism.	Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan 2001	(0)	2001
	Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe. Speech recognition chip for monosyllables.	Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan 2001	(0)	2001
	Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe. An application specific Java processor with reconfigurabilities.	Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan 2000	(0)	2000
	Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe. Multi-clock path analysis using propositional satisfiability.	Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan 2000	(0)	2000
	Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe. Waiting false path analysis of sequential logic circuits for performance optimization.	ICCAD 1998	(0)	1998

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