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Author information
First name:
Lars
Last name:
Bengtsson
DBLP:
85/2581
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Below you find the publications which have been written by this author.
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Andreas Persson
,
Lars Bengtsson
.
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems.
Signal Processing Systems 2009, Volume 56
(0)
2009
Åke Walldius
,
Yngve Sundblad
,
Lars Bengtsson
,
Bengt L. Sandblad
,
Jan Gulliksen
.
User certification of workplace software: assessing both artefact and usage.
Behaviour IT 2009, Volume 28
(0)
2009
Björn Nilsson
,
Lars Bengtsson
,
Bertil Svensson
.
Selecting back off algorithm in active RFID CSMA/CA based medium-access protocols.
IEEE Third International Symposium on Industrial Embedded Systems - SIES 2008, Montpellier / La Grande Motte, France, 11-13 June 2008 2008
(0)
2008
Minh Quang Do
,
Mindaugas Drazdziulis
,
Per Larsson-Edefors
,
Lars Bengtsson
.
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA 2007
(0)
2007
Björn Nilsson
,
Lars Bengtsson
,
Per-Arne Wiberg
,
Bertil Svensson
.
Protocols for Active RFID - The Energy Consumption Aspect.
IEEE Second International Symposium on Industrial Embedded Systems - SIES'2007, Hotel Costa da Caparica, Lisbon, Portugal, 4-6 July 2007 2007
(0)
2007
Andreas Persson
,
Lars Bengtsson
.
Reverse conversion architectures for signed-digit residue number systems.
International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece 2006
(0)
2006
Minh Quang Do
,
Mindaugas Drazdziulis
,
Per Larsson-Edefors
,
Lars Bengtsson
.
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA 2006
(0)
2006
Niklas Therning
,
Lars Bengtsson
.
Jalapeno: secentralized grid computing using peer-to-peer technology.
Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005 2005
(0)
2005
Andreas Lindahl
,
Lars Bengtsson
.
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.
Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal 2005
(0)
2005
Minh Quang Do
,
Per Larsson-Edefors
,
Lars Bengtsson
.
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings 2004
(0)
2004
Anders Lindström
,
Michael Nordseth
,
Lars Bengtsson
,
Amos Omondi
.
Arithmetic Circuits Combining Residue and Signed-Digit Representations.
Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings 2003
(0)
2003
Minh Quang Do
,
Lars Bengtsson
,
Per Larsson-Edefors
.
DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.
The 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), February 10-13, 2003, Innsbruck, Austria 2003
(0)
2003
Lars Bengtsson
.
A VLSI Array Architecture for Artificial Neural Networks.
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, NCI 2003, May 19-21, 2003, Cancun, Mexico 2003
(0)
2003
Stefan Lund
,
Lars Bengtsson
.
Synchronizing a High-Speed SIMD Processor Array.
Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland 2001
(0)
2001
Lars Bengtsson
.
Clock Speed Limitation and Timing in a Radar Signal Processing Architecture.
Signal and Image Processing (SIP), Proceedings of the IASTED International Conferences, October 18-21, 1999, Nassau, The Bahamas 1999
(0)
1999
Lars Bengtsson
,
Kenneth Nilsson
,
Bertil Svensson
.
A processor array module for distributed, massively parallel, embedded computing.
Microprocessing and Microprogramming 1993, Volume 38
(0)
1993
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16
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