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    Journal
    Name: Computer Architecture Letters
    Year: 2017
    Volume: 16
    Number: 1
    DBLP: db/journals/cal/cal16.html
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    Below you find the publications assigned to this venue.

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    Conference paper
    David A. González Márquez, Adrián Cristal, Esteban E. Mocskos.
    Mth: Codesigned Hardware/Software Support for Fine Grain Threads.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    WonJun Song, Hyungjoon Jung, Jung Ho Ahn, Jae W. Lee, John Kim.
    Evaluation of Performance Unfairness in NUMA System Architecture.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta.
    Measuring the Impact of Memory Errors on Application Performance.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Xia Zhao, Yuxi Liu, Almutaz Adileh, Lieven Eeckhout.
    LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Patrick Judd, Jorge Albericio, Andreas Moshovos.
    Stripes: Bit-Serial Deep Neural Network Computing.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, Onur Mutlu.
    LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Hoda Naghibi Jouybari, Nael B. Abu-Ghazaleh.
    Covert Channels on GPGPUs.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Ali Yasoubi, Reza Hojabr, Mehdi Modarressi.
    Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Gokul Subramanian Ravi, Mikko H. Lipasti.
    Timing Speculation in Multi-Cycle Data Paths.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Conference paper
    Young Hoon Son, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn.
    SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.
    Computer Architecture Letters 2017, Volume 16 (0) 2017
    Show item 1 to 10 of 41  

    Your query returned 41 matches in the database.